Branch Prediction Explainer
Branch prediction lets a processor continue preparing work before it knows which instruction a conditional decision will choose. Deep pipelines fetch, decode, rename, and schedule instructions in stages. If every branch forced those stages to wait until a comparison finished, much of the processor would sit idle. A predictor guesses whether the branch will be taken and, when needed, where it will go. The front end fetches from that path speculatively. If the guess is correct, useful work is already in flight.
The simplest prediction can follow a fixed rule, such as assuming a backward branch is a loop that will repeat. Modern processors learn from recent behavior. Tables indexed by parts of the instruction address store small counters that favor taken or not taken. Global-history predictors consider the outcomes of earlier branches because program decisions can be correlated. Local-history structures learn the repeating pattern of one branch. Hybrid predictors compare several mechanisms and choose whichever has recently been more accurate.
Direction is only part of the problem. A taken branch needs a target address quickly. A branch target buffer remembers destinations seen before so fetching can redirect without waiting for full instruction decoding. Return-address stacks predict where a function return will resume. Indirect branches, whose target is computed at runtime, may use specialized history because one instruction can jump to several functions or virtual methods. All these structures trade silicon area and energy for fewer bubbles in the pipeline.
Predicted instructions can execute before the branch is resolved, but their architectural results are not committed immediately. The processor tracks them in an ordered structure. When the prediction proves correct, instructions retire normally. When it is wrong, younger speculative work is discarded, registers and control state are restored to the correct path, and fetching restarts at the real target. That flush costs cycles and wastes energy, so a rare hard-to-predict branch can limit performance in a tight loop.
Compilers shape branches too. They arrange likely paths, replace some control decisions with conditional operations, inline functions, and use profile data to improve layout. Programmers can help by organizing data so conditions are predictable or by using algorithms with fewer dependent branches, but manual tricks are processor-specific and can hurt readability. A branchless expression is not automatically faster if it performs much more work or blocks other optimizations.
Speculation has security implications because discarded instructions can still affect microarchitectural state such as caches and predictors. Attacks may infer secrets from those side effects even though architectural results were never committed. Hardware and software mitigations restrict certain speculation, isolate predictor state, add barriers, or restructure sensitive code. These defenses can reduce performance because they deliberately limit the freedom that prediction was designed to create. Correctness and confidentiality are separate requirements.
Branch prediction is therefore an informed wager made by the instruction front end. History tables estimate direction, target structures estimate destination, and speculative execution fills the machine with work. Retirement makes correct-path results permanent; recovery erases mistakes. The feature does not change what the program is supposed to compute. It reduces waiting by betting on likely control flow, and its benefit depends on how accurately recurring program behavior can be compressed into fast hardware state.
Simultaneous multithreading, often called SMT, lets one processor core keep track of more than one execution thread. It can use otherwise idle parts of the core when one thread is waiting.
The core maintains separate architectural state for each thread but shares many internal resources such as execution units and caches. Hardware chooses instructions from available threads each cycle.
Threads can compete for the same cache space, bandwidth, or execution units. Performance depends on the workload, and some tasks gain little when the extra thread adds contention.
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